The LDPC encoder generates code words of the specified block length n for an binary information sequence of length k based on Parity Check Matrix (PCM) that has very low density of 1’s per rows and columns. The remaining elements of PCM are all 0’s. This LDPC has code rate of k/n and block length of n. The dimension of the PCM is (n-k)xk. The LDPC decoder IP core implements the min-sum-offset algorithm to decode LDPC codes.
The core accepts soft information that is stored in memory and generates decoded information bits. The maximum number of iterations used in the decoding of LDPC codes is fed as input. Decoding is stopped when maximum iterations are reached or when code word is decoded without any errors.
- Supports all code rates and block lengths of LDPC defined in 802.16e(WiMax), 802.11n(WLAN) and DVB-S2 standard.
- Encoder for several code rates and block lengths.
- Decoder is based on a highly flexible and scalable Architecture.
- Decoder is based on Min-Sum-Offset Algorithm.
- Compiles for any bit-width of LLR (soft information).
- Based on unique patent pending Architecture.
Block Diagram of the LDPC Coder/Decoder IP Core