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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
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LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
YEESTOR’s LDPC IP Core (Alcyone) delivers industry-leading error correction performance to support 2S/3D SLC/MLC/TLC/QLC NAND for each application from mobile, client, and enterprise NAND flash controller markets. Alcyone provides a highly efficient pure hardware engine with standard AXI interface for easily integration. Based on several patented technology of YEESTOR, the Alcyone LDPC IP provides very high throughput and error correction capability with low area and power consumption. YEESTOR’s LDPC IP was silicon-proven in industrial/enterprise PCIe SSD, USB, and EMMC application.
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Block Diagram of the LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
