The 10GBase-R Ethernet  Medium Access Controller and Physical Coding Sublayer Core provides protocol support for 10Gb/s fiber-optic transmission using Xilinx Series 7 FPGAs.
The best-in-class true 16-bit SDR datapaths and interfaces clocked at 625 MHz feature the lowest latency currently available on FPGAs. That is 12 cycles (19.2ns) in TX-direction from the user-data input (client_data_i) to the TX-FIFO and 6 cycles (9.6ns) from the RX-FIFO to the user-data output (client_data_i). The additional FIFO latency depends on actual PMA/PCS clock phase alignment and current GTH Gearbox sequence.
Both TX and RX datapaths are clocked with independent 625MHz clocks. An optional
elastic buffer is available.
The core is FPGA proven: Tested for weeks in a row without a single error on a Xilinx VC709 board connected to an Arista 7050T-64 switch.
* Configurable RX elastic buffer for ease of use: Single client-side clock domain
* 16 bit UDP/IP framer
* 16 bit TCP/IP framer
* 32 bit interface adapter for simple connection to 3rd -party upper-layer cores.