The 10GBase-R Ethernet  Medium Access Controller and Physical Coding Sublayer Core provides protocol support for 10Gb/s fiber-optic transmission using Xilinx Series 7 FPGAs.
The best-in-class true 16-bit SDR datapaths and interfaces clocked at 625 MHz feature the lowest latency currently available on FPGAs. That is 12 cycles (19.2ns) in TX-direction from the user-data input (client_data_i) to the TX-FIFO and 6 cycles (9.6ns) from the RX-FIFO to the user-data output (client_data_i). The additional FIFO latency depends on actual PMA/PCS clock phase alignment and current GTH Gearbox sequence.
Both TX and RX datapaths are clocked with independent 625MHz clocks. An optional
elastic buffer is available.
The core is FPGA proven: Tested for weeks in a row without a single error on a Xilinx VC709 board connected to an Arista 7050T-64 switch.
* Configurable RX elastic buffer for ease of use: Single client-side clock domain
* 16 bit UDP/IP framer
* 16 bit TCP/IP framer
* 32 bit interface adapter for simple connection to 3rd -party upper-layer cores.
- Automatic frame check sequence (FCS) insertion and checking
- Local Fault and Remote Fault Signaling
- Preamble insertion
- Supports arbitrary frame lengths
- 64/66 Encoder and Decoder (clause 49.2.4)
- Scrambler and Descrambler (clauses 49.2.6 and 49.2.10)
- Block synchronization (clause 49.2.9)
- clock generation (MMCM), reset synchronization, TX/RX CDX
- usable with standard GTH-Wizard wrapper for 10GBase-R (32 bit interface)
-  IEEE 802.3TM-2012 – IEEE Standard for Ethernet
- + TX-latency: 19.2ns (12 cycles @ 625MHz) + FIFO
- + RX-latency: 9.6ns (6 cycles @ 625 MHz) + FIFO
- + ready to start with example design!
- + all constraints and infrastructure included!
- Design Files: Verilog and SystemVerilog
- Example Design: Verilog and SystemVerilog
- Test Bench: SystemVerilog
- Constraints File: XDC and TCL placement
- Simulation: SystemVerilog
- Design Entry: Vivado 2015.1
- Simulation: ModelSim 10.3D
- Synthesis: Vivado 2015.1
Block Diagram of the Least-Latency 10GBase-R Ethernet MAC/PCS Core