Lightweight Configurable Display Controller
IQ-DispLite is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. All display settings (timing parameters, resolution, color depth) can be configured by software at run-time.
The IP core can be additionally scaled down at compile time by reducing bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispLite for a specific configuration.
The core has been rigorously tested in functional simulation and actual hardware. The core is accompanied with an automated testbench with a display simulation model and a memory simulation model. The memory model can be initialized with the desired bitmap through simple software provided with the model.
This core is marked as "AMPPSM Approved" and "SOPC Builder Ready".
The "AMPPSM Approved" mark indicates that this core meets Altera's sales standards and that this core has passed rigorous engineering testing.
The "SOPC Builder Ready" mark indicates that this core features plug-and-play integration with Altera's SOPC builder and the Nios® II processor over the Avalon® system interconnect.
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