LIN interface provides full support for the LIN synchronous serial interface, compatible with LIN 2.2A specification. Through its LIN compatibility, it provides a simple interface to a wide range of low-cost devices. LIN IIP is proven in FPGA environment. The host interface of the LIN can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
- Implemented in Unencrypted Verilog, VHDL and SystemC
- Supports Low Latency DRAM memory devices from all leading vendors.
- Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specifications.
- Supports programmable clock frequency of operation.
- Supports for all Mode registers programming.
- Supports all the Low Latency DRAM commands as per the specs.
- Supports for Programmable burst lengths.
- Checks for following
- -> Check-points include power on, Initialization and power off rules,
- -> State based rules, Active Command rules,
- -> Read/Write Command rules etc.
- -> All timing violations.
- Support for Power Down features.
- Support for Self Refresh features.
- Fully synthesizable
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The LIN interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.