Line Driver Differential Current Amplifier IAMP 210MHz
The IAMP has a gain range of -24dB to +1dB. At the 0dB setting the IAMP provides a nominal power of 4dBm into a 100Ω terminated line via a centre-tapped 1:1.25 transformer (centre tap at 3.3V) with a near-end termination resistance of 73.2Ω. In this case the output voltage swing at each of the differential output pins of the IAMP is between 1.9V and 4.7V
For good linearity the IAMP is biased with a DC standing current to ensure that the IAMP mirror transistors do not turn off at maximum signal excursions. The value of this standing current can be programmed to allow a trade-off of power and linearity.
The IAMP supports a “soft-start” mechanism to eliminate any transients when activating/de-activating it due to the large current drawn by the IAMP.
This block has a narrowband and wideband power mode.
View Line Driver Differential Current Amplifier IAMP 210MHz full description to...
- see the entire Line Driver Differential Current Amplifier IAMP 210MHz datasheet
- get in contact with Line Driver Differential Current Amplifier IAMP 210MHz Supplier
Block Diagram of the Line Driver Differential Current Amplifier IAMP 210MHz

Line IP
- Line Driver Differential Current Amplifier IAMP 100MHz
- An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.
- Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process
- Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
- E1/T1 Line Interface Unit / Framer
- Line driver 0.5A - TowerJazz 0.18um