4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
Linear regulator with ultra low quiescent current for retention applications
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Block Diagram of the Linear regulator with ultra low quiescent current for retention applications
![Linear regulator with ultra low quiescent current for retention applications Block Diagam](http://www.design-reuse.com/sip/blockdiagram/40034/9-main-Linear-regulator-with-ultra-low-quiescent-current-for-retention-applications.png)
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL