The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB. It supports the LMB bus protocol and byte enable architecture. Any access size up to the width of the LMB data bus is permitted. The LMB BRAM Interface Controller is the interface between the LMB and the BRAM block peripheral. A BRAM memory sybsystem consists of the controller along with the actual BRAM components that are included in the BRAM block peripheral.
- LMB v1.0 bus interfaces with byte enable support
- Used in conjunction with BRAM block peripheral to provide fast BRAM memory solution for MicroBlaze™ ILMB and DLMB ports
- Supports byte, half-word, and word transfers
- Supports optional BRAM error correction and detection
- Supports multiple LMB masters
- Support for extended address up to 64 bits