The UltraSoC Lockstep Monitor is a hardware-based, scalable lockstep solution that supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and voting with any number of cores or subsystems.
The UltraSoC Lockstep Monitor be used to verify the operation of systems based on any processor architecture, custom logic or accelerators. It consists of a set of configurable semiconductor IP (SIP) blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution and even register states, between two or more redundant systems. It can be used with any processor architecture, including those which lack native support for lockstep configurations. Because it is implemented in hardware, it responds at wire speed and imposes no execution overhead on the host system.
Unlike traditional approaches, the UltraSoC Lockstep Monitor includes flexible, run-time configurable embedded intelligence, allowing the SoC designer to tailor the monitoring and response system precisely to the application. Monitoring can be implemented at a variety of levels of granularity: at the subsystem level (comparing the outputs of the two processors); at the transaction level (for example comparing bus traffic); at the instruction level, using UltraSoC’s advanced instruction trace capability; and at the most fundamental hardware-level, checking processor internal states or register contents.
By embedding intelligence in the system, UltraSoC also allows more sophisticated comparisons between the operation of the lockstep processors than can be achieved with traditional solutions. For example, if the lockstep processors share a memory space, they cannot operate in perfect, cycle-by-cycle synchronization. UltraSoC’s on-chip analytics can be used to correlate activity within the redundant processors, and to tailor the response of the system depending on the nature of any detected anomalies.
RISC-V is gaining increasing traction in safety-critical applications, particularly in the automotive industry. However, the RISC-V ecosystem as a whole currently lacks support for the functional safety and security principles – such as lockstep operation – mandated by global standards such as ISO26262 for functional safety, J3061 for cybersecurity, IEC 61508, EN50126/8/9 and CE 402/2013. UltraSoC’s Lockstep Monitor allows any RISC-V system, whether using open source or commercial cores, to incorporate sophisticated safety capabilities.
- Configurable IP suite
- On-chip hardware monitors delivered as SIP
- Lockstep access filter to monitor system interconnect
- Lockstep bus monitor
- Trace recorder
- Status monitor
- Message infrastructure / required communicators
- Verify operation at any level
- CPU register state
- Bus transactions
- Heterogeneous: monitor ANY block; processor (including those lacking native lockstep support), accelerator (eg ADAS), custom logic
- Wire speed
- Monitor ANY number of redundant blocks
- Parametrizable soft cores
- Military and aerospace
- Functional safety
Block Diagram of the Lockstep Monitor IP Core