The Xilinx DisplayPort® solutions include DisplayPort LogiCORE™ and DisplayPort TX and RX subsystems. These solutions help users implement DisplayPort video interface as defined by VESA DisplayPort v1.2 specification. DisplayPort is a high-speed serial interface standard supported by industry leaders in consumer electronics HDTV, PC laptop and PC monitors. This protocol is considered a successor to VGA and DVI standards with support for video resolutions greater than (>4Kx2K) video and adds audio.
DisplayPort LogiCORE IP supports UltraScale™ and 7-Series Xilinx FPGAs.
To help users in creating video solutions with DisplayPort interfaces, Xilinx offers prepackaged subsystems for DisplayPort transmit and DisplayPort receive. These subsystems integrate commonly used functions with video interfaces such as video timing generation, AXI bridges and optional HDCP function with DisplayPort LogiCORE and work out of the box.
Xilinx plans to obsolete the standalone DisplayPort LogiCORE in Vivado release 2017.2 and hence users are strongly recommended to use DisplayPort Subsystems for all new designs.
- Subsystem offerings for out of the box use
- Source (Tx ) and Sink (Rx) controllers perform encoding/decoding
- SST and MST support
- One, two or four pixel-wide main link for up to 4096x2048 monitor resolution, Quad pixel allows user to get up to 600 Mhz Video Pixel clock
- Enhanced Color formats for luminance only mode & gray scale video users
- Parameterized Bits Per Color
- Auto lane rate and width negotiation (1.6 or 2.7 or 5.4 Gbps; 1, 2 or 4 lanes)
- HD video and optional de/interlace of secondary audio support up to 8-channel
- 8b/10b encoding and scrambling to reduce EMI
- DisplayPort Source and sink Reference Designs
- Sink and Source SW drivers implementing
- Link and Stream policy makers
- topology discovery and management
- Payload management and virtual channel mapping
- EDID parsing and DPCD
- Optional HDCP support