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LogiCORE IP Serial RapidIO Gen 2
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer core. This IP solution is provided in netlist form with supporting example design code. The Gen 2 IP supports 1x, 2x, and 4x lane widths. It comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design, which allows complete flexibility in selection functional blocks needed for a given application. This solution supports Verilog design environment. This IP core utilizes AXI-4 Streaming interface for data path and AXI-4 Lite interface for configuration (maintenance) transactions. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.
For Serial RapidIO Gen 1.3 (with extensions for Gen 2 5G line rates) Xilinx LogiCORE IP, please visit Serial RapidIO LogiCORE IP
For Serial RapidIO Gen 1.3 (with extensions for Gen 2 5G line rates) Xilinx LogiCORE IP, please visit Serial RapidIO LogiCORE IP
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Interface and Interconnect IP
- FlexNoC Network on Chip SoC Interconnect IP
- Cache Coherent Interconnect
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Configurable PCI Express 1.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core