MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
Lossless & Near-Lossless JPEG-LS Decoder
The decoder core can decompress any JPEG-LS stream or JPEG-LS payload of image container formats, such as DICOM (Digital Imaging and Communications in Medicine). It accepts compressed streams of images with up to 16-bit per color samples and up to four color components, in all widely used color subsampling formats. Supporting oversize image dimension parameters, the core can decode image with resolutions exceeding 64k x 64k pixels.
The easy-to-use JPEG-LS-D core operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. Application (APP) or comment (COM) marker segments—which are typically used to embed metadata in the compressed stream—are also passed to the system via a dedicated interface.
SoC integration is straightforward thanks to standardized AMBA® interfaces. The core accepts compressed data and outputs pixel data, frame format information, and APP or COM marker segments via AXI4-Stream interfaces, and it provides access to its control and status registers via a 32-bit APB interface. A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.
The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model.
This core can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
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