The S3REG40022T40LP is a regulator circuit which has been designed to provide 0.8-2.5V with a load current of up to 400mA. The output voltage is programmable.
The S3REG40022T40LP is a regulator circuit that features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output in both low-drop and high-drop operation, while maintaining minimum ripple on supply lines in the presence of
large load current spikes inherent with switching loads, e.g. highspeed ADCs.
- 40nm TSMC Logic LP Process, 7 Metals Used
- (No Analog Options) with Deep-Nwell
- 2.3V – 3.2V Input Voltage
- 0.8V – 2.5V 3% Output Voltage
- 400mA Load Current
- 200mV Drop Out Voltage
- Sleep Mode for low quiescent current
- Die Area Pre-shrink: 0.3mm2
- Leakage Via Pass Device : 60nA
- Programmable Output Voltage
- Power Down Mode
- The S3REG40022T40LP has been designed to allow low-drop operation (the PMOS pass device has been scaled for a voltage drop of 200mV). To achieve these goals, the S3REG40022T40LP requires a 4.7F external ceramic capacitor.
- The S3REG40022T40LP uses 2.5V thick oxide devices from a standard 40nm logic process. The circuit can be scaled for a range of load currents and the output voltage level is programmable. For maximum flexibility, the user can adjust the regulated output voltage if the S3REG40022T40LP is placed on a different chip.
- The S3REG40022T40LP is readily portable to other manufacturing processes or can be customised for specific customer requirements and it’s designed with the Deep-Nwell process option.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- General Purpose Low Drop Out Voltage Regulator
Block Diagram of the Low Drop Out 400mA Regulator IP Core