Low-Latency 10/100/1000 Ethernet MAC
The core supports full-duplex operation, supports jumbo frames, provides statistics counters, and it is easy to integrate and implement. The LLEMAC-1G exchanges data with the host system via a byte-wide streaming interfaces, and connects to the external PHY via an MII, GMII or RGMII interfaces. An independently clocked, 32-bit wide memory mapped interface provides access to the cores control and status registers. The default core interfaces comply to the Avalon standard, but AMBA™ AHB or AXI can also be made available upon request.
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Block Diagram of the Low-Latency 10/100/1000 Ethernet MAC IP Core

Emac IP
- 10G_TCP+UDP_Offload+EMAC+PCIe+Host_IF Ultra-Low Latency (SXTOE+UOE+PCIe)
- 10/100/1000 M bit EMAC + Host_IF
- 10G_TCP+UDP_Offload+EMAC+Host_IF Ultra-Low Latency (SXTOE+UOE)
- 40G/50G UDP/IP Hardware Protocol Stack
- TCP Offload Engine + AMBA + Mem Ctlr
- 100G Only 320-bit Ethernet MAC + PCS @ 312.5MHz Solution; 4x25