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Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
The Low Latency Interlaken core is compliant with the Interlaken 1.2 and Interlaken look-aside 1.1 specifications.
The System BusWidth, Core BusWidth, and Lane Count are configurable. The System BusWidth is configurable from 1 Word to 16 Words, the Core BusWidth is configurable from 1 Word to 8 Words, and the LaneCount is configurable from 1 Lane to 32 Lanes. Note, 1 Word is 8 bytes.
The core runs cycle accurate, and is designed to run at 390 MHz in Altera SV-3. Every word delivers 25G of bandwidth, e.g. a solution with a 1 Word core can service 4x6.25G. Note, the Core bandwidth has to be equal to or greater than the SerDes bandwidth. The user transmit and receive interfaces are through asynchronous FIFOs, which completely decouple the user clock domain from the cores clock domain.
The System BusWidth, Core BusWidth, and Lane Count are configurable. The System BusWidth is configurable from 1 Word to 16 Words, the Core BusWidth is configurable from 1 Word to 8 Words, and the LaneCount is configurable from 1 Lane to 32 Lanes. Note, 1 Word is 8 bytes.
The core runs cycle accurate, and is designed to run at 390 MHz in Altera SV-3. Every word delivers 25G of bandwidth, e.g. a solution with a 1 Word core can service 4x6.25G. Note, the Core bandwidth has to be equal to or greater than the SerDes bandwidth. The user transmit and receive interfaces are through asynchronous FIFOs, which completely decouple the user clock domain from the cores clock domain.
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Block Diagram of the Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
