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Low Noise PLL
Features
- TSMC 90nm G Logic
- 1.2V Power Supply
- Comparison Frequency: 20MHz
- VCO Frequency: 750MHz
- Two Output Clocks: 375MHz and 250MHz
- Programmable Reference Divider
- Long Term Jitter: < 5ps-rms
- Low Power Dissipation
- Power-Down and Bypass Modes
- No External components
- Compact Die Area
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Low Noise PLL
- Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
- Ultra Low Area Frequency Synthesizer PLL (5nm - 90nm)
- Ultra-Low-jitter Ring PLL
- Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks, DELTA standard
- Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks, DELTA standard
- Low Noise Fractional PLL in TSMC 65nm LP