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MIPI D-PHY Transmitter - Designed for TSMC 40nmLP for Automotive
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Low Noise Programmable PLL
This customisable PLL has been designed for use with high-performance A/D converters where low jitter clock generation is critical to the success of applications such as DVB, Cable Modem and Wireless LAN.
An integer N type PLL is used yielding excellent phase noise performance. The PLL is designed to provide excellent jitter performance while also maintaining low current consumption. It uses a third order loop filter which gives very good spurious performance, supply rejection, phase noise and jitter performance.
An integer N type PLL is used yielding excellent phase noise performance. The PLL is designed to provide excellent jitter performance while also maintaining low current consumption. It uses a third order loop filter which gives very good spurious performance, supply rejection, phase noise and jitter performance.
Features
- 65nm SMIC Logic Low Leakage Process
- Deep NWELL included for noise isolation
- Single 1.2V Power Supply Voltage
- Input Frequency Range: 10MHz – 150MHz
- Comparison Frequency Range: 10MHz – 50MHz
- VCO Frequency Range: 600MHz – 1200MHz
- 4 Independent Programmable Output Clocks
- Output Clock Range 4.72MHz – 600MHz
- Power Down and Bypass Mode
- Low Jitter < 15ps rms
- Power Dissipation ~ 5.2mW
- No External Components Required
- Compact Die Area
- 55nm Shrink compatible
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