E804 utilizes a 3 to 4-stage variable-length pipeline and a scalar DSP computing engine, and can be optionally equipped with a floating point unit and secure execution technology to enhance system security. It is suitable for application fields with certain requirements on computing power, such as audio, voice, and motor control.
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 3 to 4-stage variable length pipeline;
- General register: 32 32-bit GPRs;
- Bus interface: Tri-bus (instruction bus + data bus + system bus);
- Memory protection: 0 to 8 optional protection zones;
- Tight coupling IP: Interrupt controller and timer;
- Floating point engine: Optional single-precision floating point unit;
- DSP engine: scalar DSP engine, supporting 8-bit/16-bit/32-bit data types;
- Secure execution technology: Resists any hardware and software attacks, and increases system security;
- Low-power cache: Reduces system memory access latency, and improves memory efficiency;
- Dynamic adjustment of interrupt priority: Enhances real-time performance of the system, and implements interrupt priority inversion in specific scenarios;
- Cycle acceleration technology: Improves the processing capacity of short cycle programs, and eliminates branch performance loss;
- Data prefetching technology: Improves bus bandwidth utilization, and adapts to large data application scenarios.
- Speech Recognition;
- Industrial Control.
Block Diagram of the Low power 32-bit processor with lightweight computing power