Root of Trust IP Meeting Automotive Functional Safety Standards
Low-power 32-bit RISC-V processor
RV32IMC open-instruction set architecture (ISA) defined
by the RISC-V foundation and, as such, is supported
by standard state-of-the-art development
tools (both open-source and proprietary). The 4-stage
pipeline is optimized for power and area efficiency.
Additional customizations are available on demand
(e.g. RV32E area efficient implementation).
The icyflex-V core targets traditional micro-controller
applications and is well suited for IoT, wearables and
mixed signal applications.
The core IP comes along with various bus interconnect
IP’s and standard peripherals. For example, implementations
relying on an embedded flash will benefit from
an energy oriented cache architecture.
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Block Diagram of the Low-power 32-bit RISC-V processor IP Core
32-bit RISC-V processor IP
- 32-bit Embedded RISC-V Functional Safety Processor
- Ultra-Low-Power Deeply Embedded RISC-V Processor
- 32 bit - Compact RISC-V Processor Core
- 32 Bit - Embedded RISC-V Processor Core
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)