The ADC is a fully differential 9-bit cyclic ADC which utilizes 4-bit binary weighted array to obtain 9-bit resolution. Cyclic algorithm for the ADC conversion is used to reduce number of capacitors in the capacitor array and save layout area. The ADC is designed for suppression of the supply variation, even in the conversion cycle.
- The ADC conversion is divided into three phases. In each of the phases three bits are obtained; in Phase I the three most significant bits are obtained (MSBs), in Phase II the three middle bits and in Phase III the three least significant bits (LSBs). The voltage swing at the output of the operational amplifier is adaptive and it depends on the conversion phase, accounting for the drop of supply voltage during the conversion cycle. Operational amplifier has a built-in slew rate (SR) detection circuit which dynamically controls the amplifier current and optimizes power consumption and speed.
- Low power consumption, insensitivity to power supply variations
- Schematic and layout design(GDS) for chosen 180 nm technology
- Low power applications, low sampling rate, ADC, energy harvesting systems
Block Diagram of the Low power 9 bit cyclic ADC IP Core