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Low-power, high-speed 11-bit SAR ADC on TSMC 28nm HPC+
The A11B4G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a hybrid successive approximation register (SAR) ADC, with a 11-bit resolution, and a sampling speed of 4 gigasamples per second (GSPS).
The advanced IP block has been designed for the TSMC 28nm HPC+ process to provide superior performance/power specifications.
The cost-effective IP block has been designed and verified for TSMC HPC+ processes and validated at 28 nm process.
The advanced IP block has been designed for the TSMC 28nm HPC+ process to provide superior performance/power specifications.
The cost-effective IP block has been designed and verified for TSMC HPC+ processes and validated at 28 nm process.
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