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Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
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Low Power Locked Ring Oscillator - TSMC 40nm
The SGC21370 is programmable ring oscillator optimized for clock recovery in ultra compact applications. The oscillator have been optimized for digitally controlled clock generation. The core uses internal high PSRR topology for improved robustness. It is specified from Tj = -40ºC to +125ºC
Features
- Programmable Ring Oscillator
- Fully self contained (no extra references or pins)
- Good accuracy: ± 10 %
- Stable output indicator
Deliverables
- Layout (GDSII)
- Netlist (CDL)
- Abstract (LEF)
- Timing (LIB)
- Model (Verilog)
- Datasheet
- Assembly Guidelines
Applications
- Automotive
- Communications
- Consumer Electronics
- Data Processing
- Industrial and Medical
- Military/ Civil Aerospace
- Others
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