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Low Power Multiprotocol SerDes PMA
The wide-range 0.6Gbps to 6.25Gbps 4-lane Deserializer and Serializer macros include all high-speed analog functions for four lanes of high-speed data transport between chips over FR4 and similar PCBs and over high quality cables. Trimmable on-die termination and linear equalization are included to compensate for channel loss enabling longer cables. They are optimized for low power operation and is suitable for a variety of chip-chip communication protocols.
Features
- Very wide CDR range { operates with data rates from 0.6Gbps to 6.25Gbps
- Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One
- Four lanes sharing bias to save area and power may be placed any number of times
- Switchable receiver equalization to improve signal integrity and compensate for lossy channels
- Trimmable on die termination for excellent signal integrity
- High-speed loop-back path simplifes production testing when used together with serial data sources
- Comprehensive power-down control to optimize power modes
- Small die area { only 0.14mm2/lane including pads
- 1.8V I/O voltage operation
- Auxiliary output dividers (1/30,1/40,1/50) for compatibility with multiple PCS designs
Deliverables
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- LEF
- Application Note with integration and production test guidelines
Applications
- UHD-TV (4k TV) displays
- MFPs
- Scanners
- Semi-custom chip-chip interfaces
- Low power backplanes
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