Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ac- coupled high-speed serial communication standards requiring serial Clock Data Recovery (CDR). The pin-configurable macro uses standard logic process devices, and exhibits exceptional input sensitivity, input jitter tolerance and low output jitter. Analog Bits proprietary and industry leading PLL technology in combination with sophisticated circuit techniques and innovative IO design makes this macro an extremely area and power efficient solution. The PMA can be integrated with the available PCS to provide a PCI-Express Gen1/Gen2 PHY solution, and has interface capability to allow integration with other customer-designed serial protocol PCS layers.

• see the entire Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC datasheet
• get in contact with Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC Supplier