400MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
LPDDR 3/2 DDR 3/3L 1600 PHY SMIC 28HK
The PHY IP is engineered for quick and easy integration into system-on-chips (SoC), and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. The PHY IP provides a DFI-compliant memory controller interface.The PHY IP is validated with multiple hardware platforms for reduced risk and is designed to be interoperable with various supplier memory chips.
The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.
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