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LPDDR 4/3/2 DDR 4/3/2 Combo PHY SMIC28PS
The DDRn IP Mixed-Signal LPDDR2/LPDDR3/DDR3/DDR2 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed (up to 1333Mbps for LPDDR2/3, up to 1600Mbps for DDR3) applications with robust timing and small silicon area in 28nm process. It supports all JEDEC LPDDR2/3&/DDR3/DDR2 SDRAM components in the market. The PHY components contain DDR specialized functional and utility SSTL and HSUL_12 I/Os from 200Mbps up to 1600Mbps (DDR3) in 28nm, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.
Features
- LPDDR2/3 and DDR3 modes & signaling&,rates from 200Mbps up to 2667Mbps,respectively
- x16/x32 data path interface extendable
- 1.2V/1.5V/1.8V JEDEC standard
- SSTL, HSUL_12 I/Os supported
- Multiple drive strengths adjustable
- Independent read and write timing adjustments with auto calibration
- Low latency with programmable timings for secure data handling
- Per bit deskew support (optional)
- Supports point to point memory sub systems and multi-rank
- PVT compensation and timing calibration for all corner reliability
- At speed BIST, boundary scan
- Various power-down modes for low power including self-refresh support
- Low jitter with superior noise rejection
- APB Port register access interface
- Dual Row IO implementation and more
- Implemented using 1.05V RVT&LVT core devices and 1.8V gate oxide IO devices
- Supports both wire-bond and flip- chip packaging
- Wire-bond speed is package limited
Benefits
- Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
- Zero risk with robust ESD architecture
- Maintains self-refresh I/O drive state during VDD power down
- Extensive EDA tool support for various design automation flows
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
- DFI2.1 compliant memory controller interface (DFI3.1 option)
- Flexible pad ring configuration to adapt for various design and chip scenarios
- Integration with other INNOSILICON interface IP
- Takes full advantage of process power savings and speed capability
- Best in class low noise design to ensure best timing margin and signal integrity
- DFT functions to reduce test time and ensure high test coverage
- Several programmable PHY operating modes through simple register interface
- Per Bit De-skew to improve composite data eye during read cycles at high speed.
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