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LPDDR 4/3 3200 HS PHY TSMC 16FFLL+
The Cadence Denali Low-Power DDR PHY IP supports LPDDR4/LPDDR3, provides low latency, and enables up to 3200Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer applications, while balancing power consumption. The PHY IP is silicon proven and designed for ease of integration and faster time-to-market.
The PHY IP is engineered for quick and easy integration into system-on-chips (SoC), and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. The PHY IP provides a DFI-compliant memory controller interface.The PHY IP is validated with multiple hardware platforms for reduced risk and is designed to be interoperable with various supplier memory chips.
The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.
The PHY IP is engineered for quick and easy integration into system-on-chips (SoC), and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. The PHY IP provides a DFI-compliant memory controller interface.The PHY IP is validated with multiple hardware platforms for reduced risk and is designed to be interoperable with various supplier memory chips.
The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.
Features
- LPDDR4/LPDDR3/DDR4/DDR3 training with write-leveling and data-eye training
- Optional clock gating available for low-power control
- Memory controller interface complies with DFI standards 4.0 or 3.1
- Internal and external datapath loop-back modes
- I/O pads with impedance calibration logic and data retention capability
- Multiple PLLs for maximum system margin
- Programmable clock delay (PVT compensated) on read
- and write datapaths for DQS alignment
- Per-bit deskew on read and write datapath
Benefits
- Widest data-valid-eye
- Expanded functional testing
- Low-power control
Deliverables
- GDS II macros with abstract in LEF
- Verilog post-layout netlist
- STA scripts for use at chip or standalone PHY levels
- Liberty Timing model
- SDF for back-annotated timing verification
- Verilog models of I/O pads, and RTL for all PHY modules
- Verilog testbench with memory model, configuration files, and sample tests
- Documentation—integration and user guide, release notes
- Verification IP set up files
Applications
- Networking
- Cloud computing
- Wireless communication equipment
- Mobile devices
- Consumer products
- Automotive Infotainment
- Internet of Things Products
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LPDDR IP
- DDR and LPDDR 4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
- LPDDR4/3/2 DDR4/3/2 ComboPHY
- Universal Multiport Memory Controller - LPDDR 3/2 Controller
- DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - SMIC 40nm LL
- DDR and LPDDR 3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
- Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process