LPDDR is full-featured, easy-to-use, synthesizable design, compatible with JESD209B and JESD209A-1 specification. Through its LPDDR compatibility, it provides a simple interface to a wide range of low-cost devices. LPDDR IIP is proven in FPGA environment. The host interface of the LPDDR can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
LPDDR IIP is supported natively in Verilog and VHDL
- Supports LPDDR protocol standard JESD209B and JESD209A-1 Specification
- Compliant with DFI version 5.0 Specification
- Supports up to 2GB device density
- Supports X32 and X16 devices
- Supports all speed grades as per specification
- Supports programmable CAS latency
- Supports programmable burst length: 2, 4, 8 and 16
- Supports Mode registers/Control programming
- Supports extended mode register programming
- Supports burst type: Sequential and Interleave
- Supports burst order
- Supports write data mask
- Supports power down features
- Supports deep power down features
- Supports auto precharge option for each burst access
- Supports auto refresh and self refresh modes
- Supports Multiple Outstanding transaction
- Supports In-port Arbitration using QoS
- Supports 2:1 and 4:1 Clock Ratio Modes
- Supports CRC and ECC for Write and Read Operations
- Supports 1:4 Controller to DFI PHY frequency ratio
- Supports Programmable clock frequency operation
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The LPDDR interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog or VHDL or SystemC source code.
- Integration test-bench and tests.
- Scripts for simulation and synthesis with support for common EDA tools.
- Documentation contains User's Guide and Release notes.
Block Diagram of the LPDDR Controller IP Core