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LPDDR2 Memory Controller
The Cadence Denali Controller IP for LPDDR2 is a configurable LPDDR design with the ability to support a wide range of high-bandwidth memory applications.
It includes sophisticated engines to rearrange transactions and maximize memory bus utilization. Programmable arbitration algorithms allow for multiple ports to share the memory bus efficiently. The Denali Controller IP for LPDDR2 is configurable to meet specific data profiles and enables performance optimization for an individual system and memory requirements.
It includes sophisticated engines to rearrange transactions and maximize memory bus utilization. Programmable arbitration algorithms allow for multiple ports to share the memory bus efficiently. The Denali Controller IP for LPDDR2 is configurable to meet specific data profiles and enables performance optimization for an individual system and memory requirements.
Features
- Fully configurable for performance, power, gatecount, and multi-port data arbitration
- Advanced page policy engine and transaction reordering insures high bandwidth utilization can be met across a range of applications
- Multiple arbitration options allow for prioritization of initiators, and guarantees quality of service
- Advanced Low-power options include all DRAM power management modes, extensive clock tree gating, and multiple power wells
- Optional ECC and built in memory system self test (BIST)
- Multiport Option
- Multiple port options with different types (AXI, AXI4, AHB, OCP, Denali), width, synchronous or asynchronous
- Supports standard DFI interface to the PHY
Benefits
- Configurable to meet specific data traffic profiles
- Optimized low latency for data-intensive applications
- Future-proof system design for emerging DDR standards
Deliverables
- Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Documentation: integration and user guide, release notes
- Sample Verification testbench with integrated BFM and monitors
Applications
- Mobile
- Consumer
- IoT
- Automotive
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