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LPDDR2 PHY
The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications. Our PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.
Features
- PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
- Autonomous initialization
- Support for x72 bit channel
- Support for multiple DRAM widths (x4, x8, x16, x32)
- Support for single channel, 1 to 4 ranksSelectable low-power operating statesDFI 3.1 compliant for easy integration with memory controllerProgrammable output impedance and on-die terminationZQ calibration of output impedance and on-die calibrationUtilizes standard 8-layer 6020 metal layer stack
Deliverables
- Fully-Characterized hard macro (GDSII)
- Complete design views
- Memory controller reference design
- Full documentation and datasheet
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LPDDR2 PHY IP
- DDR4 Multi-modal PHY
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- LPDDR5 PHY Samsung 7LPP,8/10LPP
- Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
- Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version
- Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process