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LPDDR2 PHY
The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications. Our PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.
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LPDDR2 PHY IP
- DDR4 Multi-modal PHY
- LPDDR5 PHY Samsung 7LPP,8/10LPP
- LPDDR5 PHY SMIC 7,8/10SFE,12/14SF+
- Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
- Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
- Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process