The High-Performance Memory Controller II SDRAM MegaCore® function for Quartus® II design software v11.0 handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 933 MHz. The function initializes the memory devices, manages SDRAM banks, translates read and write requests from the local interface into all the necessary SDRAM command signals, and performs command and data reordering.
The High-Performance Memory Controller II core is a drop-in replacement for the existing SDRAM controller, with many new enhanced features. New features include a quarter rate controller, 2-T command timing to maintain command channel bandwidth, 50-percent higher random access efficiency with command and data reordering, power down and self-refresh support, and error correction code (ECC) with sub-word writes.
Whether you use the IP Toolbench in Qsys or Quartus II software, it generates an example design, an example driver, and the DDR1, DDR2, and DDR3 SDRAM controller, and instantiates a phase-locked loop (PLL). This fully functional design example can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller, and checks the read data to produce the pass and fail and test complete signals. Also included is an efficiency monitor which can determine the actual bandwidth of the memory bus based on the data patterns being used.
Included in the IP Base Suite?FREE with Quartus II Subscription Edition software