LPDDR3/2 DDR3/2 Combo PHY SMIC 110/130G

The Mixed-Signal LPDDR2/DDR/DDR2/DDR3 Combo PHYs with industry standard DFI V2.1 interface provide the most advanced physical interface solutions for ICs requiring access to all sorts of JEDEC compatible SDRAM devices. It is optimized for low power and high speed (up to 400Mbps for DDR/MDDR, up to 1066Mbps for LPDDR2/DDR2 and up to 1333Mbps for DDR3) applications with robust timing and small silicon area. The PHY components contain DDR specialized functional and utility SSTL I/Os, ESD, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control. Optional memory controller is available to support AHB/AXI and FIFO interface to CPU bus.

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