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Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
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LPDDR4 Controller
The Cadence Denali Controller IP for LPDDR4 is a configurable LPDDR design with the ability to support a wide range of high-bandwidth memory applications.
It includes sophisticated engines to rearrange transactions and maximize memory bus utilization. Programmable arbitration algorithms allow for multiple ports to share the memory bus efficiently. The Denali Controller IP for LPDDR4 is configurable to meet specific data profiles and enables performance optimization for an individual system and memory requirements.
It includes sophisticated engines to rearrange transactions and maximize memory bus utilization. Programmable arbitration algorithms allow for multiple ports to share the memory bus efficiently. The Denali Controller IP for LPDDR4 is configurable to meet specific data profiles and enables performance optimization for an individual system and memory requirements.
Features
- Compliant to LPDDR 4/3 and DDR 4/3/3L protocol memories
- Single and multi-port host interface options
- Flexible paging policy including auto-precharge-per-command
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc
- Priority-per command on ARM(R) AMBA(R)3 AXI and low latency Denali interface
- QoS features allow command prioritization on ARM AMBA4 AXI interfaces
- Silicon proven and shipping in volume
Benefits
- Configurable to meet specific data traffic profiles
- Optimized low latency for data-intensive applications
- Future-proof system design for emerging DDR standards
Deliverables
- Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Documentation: integration and user guide, release notes
- Sample Verification testbench with integrated BFM and monitors
Applications
- Mobile
- Consumer
- IoT
- Automotive
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LPDDR4 Controller
- DDR Enhanced Memory Controller (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- LPDDR4 Add-On for DDR Enhanced Universal Memory Controller (uMCTL2)
- IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in LPDDR4 mode, AXI tunnel to ARC SDP
- SDRAM LPDDR4/3/2 Host Controller & PHY
- DDR3 / DDR4 / LPDDR3 / LPDDR4 Memory Controller