LPDDR4 multiPHY V2 in Samsung (14nm, 10nm)
LPDDR4X multiPHY: Compatible with JEDEC standard LPDDR4 or LPDDR4X SDRAMs up to 4,267 Mbps
DFI 4.0 Version 2 compliant interface to the memory controller: 1:1, 1:2, and 1:4 clock modes supported - Optional dual channel DFI for independent 2-channel memories (e.g., LPDDR3/4)
Flexible channel architecture: Support for two independent LPDDR4/4X 16-bit channels via one 32-bit PHYs for reduced area and power - Support for one DDR4/3 interface
Support for 8-bit, 16-bit, 32-bit and 64-bit wide SDRAMs: 8-bit and 16-bit DDR3 (LPDDR4 multiPHY only) and DDR4 supported - 16-bit per channel LPDDR4/4X supported - 16-bit and 32-bit per channel LPDDR3 supported (LPDDR4 multiPHY only)
Flexible configuration options: LPDDR4/LPDDR4X/LPDDR3: Up to 2 DQ loads, 8 CA loads, and 4 CS loads - DDR4/DDR3: Up to 4 DQ loads and 4 ranks of CA loading - Shared AC mode that permits one address and command channel to be time division multiplexed between two independent data channels
PHY independent, firmware-based training using an embedded calibration processor: Utilizes specialized hardware acceleration engines - Automatic periodic retraining through the DFI MASTER interface
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