Today’s consumers generate and consume large volumes of data and video, exploding the need for data-intensive processing requiring high memory bandwidth. The Cadence® Denali® Gen2 PHY IP for LPDDR5/4/4x for the TSMC N7 Process is a family of high-speed on-chip interfaces to external memories supporting these high-performance requirements with products that are optimized for each application's needs.
The LPDDR PHY IP is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The applicationoptimized LPDDR PHY IP can achieve speeds up to 5500Mbps. Low-power features include the addition of a VDD low-power idle state in the PHY and power efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce overall area by up to 20%.
The LPDDR PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into an SoC, and is verified with the Denali Controller IP for DDR as part of a complete memory subsystem solution. The LPDDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.