LPDDR5/4/4x PHY IP for Samsung 14nm
The ORBIT Memory system consists of interconnect, memory controller, and PHY IPs that work in unison to create maximum system synergies. The ORBIT DDR PHY (OPHY) features a state-of-art mixed-signal architecture that addresses the challenges of DRAm integration in high-performance and low-power environments. This architecture enables OPHYs to overcome issues with long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without interruption of data traffic. Programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between the ORBIT Memory Controller (OMC) and the DRAM.
OPHYs are designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage. Tight integration with the ORBIT Memory System enables ActiveQoS bandwidth and latency control for maximum performance of the SoC memory subsystem. At the system level, OPHYs have been designed to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications and application processors.
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Block Diagram of the LPDDR5/4/4x PHY IP for Samsung 14nm
- DDR and LPDDR 4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
- LPDDR4/3/2 DDR4/3/2 ComboPHY
- DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
- Universal Multiport Memory Controller - LPDDR 3/2 Controller
- LPDDR 4/3/2 DDR 4/3/2 Combo PHY SMIC28PS
- SMIC 55nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application