LPDDR5/4x/4 combo PHY on 14nm, 12nm
The LPDDR5/4x/4 Combo OPHY features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables LPDDR5/4 Combo OPHY to overcome issues with long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without interruption of data traffic. The programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between OMC and the LPDDR5/4x/4 DRAM without sacrificing performance.
The LPDDR5/4x/4 Combo OPHY was designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage.
At the system level, the LPDDR5/4x/4 Combo OPHY was designed to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications and application processors.
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