Lowest latency and highest data rates for data-intensive applications
The LPDDR PHY IP is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The application-optimized LPDDR PHY IP can achieve speeds up to 6400Mbps. Low-power features include the addition of a VDD low-power idle state in the PHY and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce overall area by up to 20%. The LPDDR PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into an SoC, and is verified with the Denali Controller IP for DDR as part of a complete memory subsystem solution. The LPDDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.