LRW-AES Core

Features

• Small size: LRW2-25.6 starts at 44,400 ASIC
• gates at throughput of 25.6 bits per clock.
• Synthesized for 550+ MHz clock speeds
• (70+ Gbps throughput for LRW2-128).
• Completely self-contained: does not require
• external memory.
• Supports both encryption and decryption.
• Includes key expansion
• Support for Liskov-Rivest-Wagner encryption and
• decryption (LRW)
• 128+128 bit LRW keys supported. See LRW3
• family for 256+128 key support.

Benefits

• The LRW2 family of cores covers a
• wide range of area / throughput combinations,
• allowing the designer to choose the smallest core
• that satisfies the desired clock/throughput
• requirements.

Deliverables

• Synthesizable Verilog RTL source code
• Testbench (self-checking)
• Vectors for testbenches
• Expected results
• User Documentation

• see the entire LRW-AES Core datasheet
• get in contact with LRW-AES Core Supplier