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LTE-A Analog Front-End (28nm)
The LTE-A Analog Front-End is a low-power and low die-area MIMO AFE for Wireless broadband applications such as LTE. The AFE can be customizable for numerous configurations such as 1x1, 2x1, 2x2. The default configuration which is 1x1 as shown includes ultra-low power SAR IQADC and a current steering IQDAC.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE. A 10-bit ADC and an 11-bit DAC are also included to perform auxiliary functions.
The LTE-A Analog Front-End operates from a 0.9V/1.8V supply, and each of the components uses architectures ideally suited for fabrication in a 28nm CMOS process and in complex SoCs.
The LTE-A Analog Front-End does not require any special analog options, and can be cost-effectively ported across foundries, different MIMO configurations and process nodes upon request.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE. A 10-bit ADC and an 11-bit DAC are also included to perform auxiliary functions.
The LTE-A Analog Front-End operates from a 0.9V/1.8V supply, and each of the components uses architectures ideally suited for fabrication in a 28nm CMOS process and in complex SoCs.
The LTE-A Analog Front-End does not require any special analog options, and can be cost-effectively ported across foundries, different MIMO configurations and process nodes upon request.
Features
- 28nm Process, 7 Metals Used
- No Analog Options
- Customizable AFE
- 1.8V and 0.9V Supplies
- Sampling Rate up to 80MS/s
- 12-bit 40MS/s IQ ADC
- 12-bit 80MS/s IQ DAC
- Low-Jitter Integer-N PLL
- Input Signal Swing 1.0Vppdiff
- 10.2-bit ENOB Typ.@ Fin=10MHz
- SFDR=70dBc Typ. @ Fout =10MHz
- Internal Bandgap and Biasing System Included
- No External Components Required
- Stand-By and Power-Down Modes
- Ultra-Low Power Consumption
- Ultra-Small Die Area
Applications
- LTE
- 802.11x
Block Diagram of the LTE-A Analog Front-End (28nm) IP Core
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