This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code achieves near optimal error-correcting performance as specified in the LTE standard with information bit lengths ranging from 40 to 6144 bits and supporting LTE different coding rates.
- 8-bit precision for input LLR.
- 13-bit precision for internal calculations.
- Provides automatic normalization for internal calculations to avoid hardware overhead.
- Supports full 3GPP-LTE and UMTS block size range is supported.
- Supports rate 1/3 coded input.
- Supports MAX-log-MAP with scaling factor.
- 8 parallel-decoding units (with options of 4/2/1 parallel decoding units for smaller block length codes).
- Sliding window algorithm for internal memory reduction.
- Uses parallel internal interleaver/de-interleaver.
- Payload throughput of up to 43.2 Mbit/s at 6 iterations (111 MHz on Xilinx-XC6VLX760-1FF1760).
- Supports configurable maximum number of iterations and controllable termination for achieving greater throughput.
- System Model (MATLAB / C code).
- Synthesizable Verilog.
- Verilog Test Benches.
- UMTS compatible