English
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
You are here:
LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm)
A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers, and supports up to 1.5Gbps data rate. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
View LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm) full description to...
- see the entire LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm) datasheet
- get in contact with LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm) Supplier
Block Diagram of the LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm)
LVDS Rx IP IP
- MIPI CSI-2 Receiver LVDS/D-PHY Combo in TSMC28HPC+
- IGALVDT08B, TSMC CLN28HPM LVDS TX/RX Combo IO
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF
- LVDS RX & TX IOs in TSMC and GlobalFoundries Technologies
- DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process