PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm)
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Block Diagram of the LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm)

LVDS Rx IP IP
- MIPI CSI-2 Receiver LVDS/D-PHY Combo in TSMC28HPC+
- IGALVDT08B, TSMC CLN28HPM LVDS TX/RX Combo IO
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF
- LVDS RX & TX IOs in TSMC and GlobalFoundries Technologies
- DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process