The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit/s LVDS Receiver and the LDP_RE_000_25V is the voltage reference for up to 16 drivers. The LDP_OU_675_25V_T is designed to drive either 50Ω or 100Ω differential termination. This cell has been designed to meet a set of the standard LVDS specifications (IEEE Std 1596.3-1996, Low Voltage Differential Signaling).
Using this LVDS Pad Set, the system can achieve very high data rates per pin with simple termination requirements and low EMI. Both driver and receiver have been optimized for speed/power and can be ported to various pure digital CMOS processes from 0.18μm down to 28nm technologies. The LDP_OU_675_25V_T has been optimized for 2GBit/s operations. The receiver has been designed with no hysteresis in order to optimize sensitivity and skew.
The driver design has all the necessary components for transmit of LVDS data and a temperature stable internal reference for setting of the LVDS signaling voltage and common mode level. This provides user flexibility in deploying multiple LVDS transmitters. The reference block is required for the LVDS drivers to provide a stable common mode voltage as well as an accurate current reference for the driver source / sink current. Maximum operating frequency is 1GHz.
- Powered from 2.5V ±10% and 1.1V to 1.2V (±10%) core power supplies
- Operates up to 1GHz (2Gbps)
- Input receive sensitivity of 75mV peak differential (without hysteresis)
- Common mode range from 0V to 2.4V (limited by Power Supply)
- Power-up sequence independent
- Power consumption is 5 mW typical and 7.5 mW maximum at 1GHz
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)