V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high performance data transmission applications.
This LVDS receiver is a very fast comparator that can recover very small differential signaling with a very wide common mode range, allowing a proper recovery of LVDS signals and its use with many other specification.
Two separate library are available: inline (VT18LVDSR-I) and staggered I/O configuration (VT18LVDSR-S).
- • 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
- • 3.3V/1.8V ±10% supply voltage, -40/+125°C temperature.
- • IEEE Standard 1596.3-1996 and ANSI/TIA/EIA-644-A Specifications.
- • Up to 1250Mb/s DDR, or 800Mhz clock.
- • Optional 100Ω on die termination ±20%.
- • Power down mode.
- • CMOS input for chip testability (JTAG…)
- • Rail to Rail Input common mode for extended compatibility with other specification.
- • Do not require extra external bias circuit.
- • Small area : [contact us]
- • Comes with a set of ESD protected power pads, corner, filler and break cells for easy integration.
- • Silicon proven, and test report available.
- - low cost solution
- - very easy to integrate
- - full support
- The library includes:
- - LVDS receiver with internal 100 Ohm termination,
- - LVDS receiver without termination,
- - a set of filler cells, power cells and corner cell,
- - GDSII
- - LVS netlist
- - LIB timing
- - LEF abstract
- - Verilog/VHDL model
- - Datasheet
- - Application Note