The S3LVDSRX500MT65 is LVDS receiver IP macro with operation frequency up to 500MHz and it is compliant with TIA/EIA-644 LVDS standard.
The S3LVDSRX500MT65 has integrated termination resistor 100Ω on-chip across its differential inputs.
The S3LVDSRX500MT65 shall be integrated together with S3LVDSBIAST65 IP macro providing the RX block with the reference voltages and power-on-control signal.
The S3LVDSRX500MT65 can be cost-effectively ported across foundries and process nodes upon request.
- 65nm TSMC Logic LP Process, 4 Metals
- 1.2V & 2.5V Supply Voltage
- Compliant with TIA/EIA-644 LVDS standard
- Operation frequency up to 500MHz (1Gbps)
- 100Ω on-chip termination resistor
- 5mA Current Consumption at 500MHz
- Power-Down mode
- Die Area: 0.02 mm2
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
Block Diagram of the LVDS Receiver, 1Gbps IP Core