The CL12482IP receiver converts serial five LVDS data streams data back into parallel 35bits (30bits of RGB data and 5bits of HSYNC, VSYNC, DE and Control1, Control2) of LVCMOS parallel. The CL12482IP receiver can be programmed for rising edge or falling edge clocks through a dedicated pin. The CL12482IP receiver is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.
- LVDS RX single
- Input Clock: 20MHz~135MHz
- Input Data Rate: 140Mbps~945Mbps
- Output Clock: 20MHz to 135MHz shift clock support
- Low power single 3.3V (Option: 2.8V)
- TIA/EIA-644 and IEEE 1596.3 compliant
- Clock edge programmable
- Supports RGB 18 / 24 / 30
- Narrow bus reduces cable size
- PLL requires no external components
- Power down mode
- ±345mV swing LVDS for low EMI
- Supports Fail-Safe function to all input channels
- Pin Compatible with THine THC63LVD104A
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP from this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file