English
You are here:
LVDS receiver, 650M, 5 channel
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution. The LVDS Receiver IP converts the LVDS data streams back into 70bits of CMOS/TTL data with a variety of LCD panel controllers.
Features
- Function compatible with the National DS90CF386
- Converts 5-pair LVDS data streams into parallel 35 bits of CMOS/TTL data
- Converts 10-pair LVDS data streams into parallel 70 bits of CMOS/TTL data with double channel
- Wide dot clock range: 25-170MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
- Supports Dual Link at up to 170MHz dot clock for UXGA
- On-chip DLL requires no external component
- Low-power CMOS design
- Power-down control function
- Compatible with TIA/EIA-644 LVDS standards
- Full industrial operating temperature range -40 ~ +85 °C
- SMIC 0.18um Logic Salicide Process (1p4m, 1.8V/3.3V)
- Off chip 100ohm resistances between receiver’s positive input and negative input
- Negative clock edge for data output
View LVDS receiver, 650M, 5 channel full description to...
- see the entire LVDS receiver, 650M, 5 channel datasheet
- get in contact with LVDS receiver, 650M, 5 channel Supplier
LVDS receiver IP
- Differential Receiver - TSMC 7FF
- Camera SLVS-EC/MIPI D-PHY/sub-LVDS/CMOS1.8 combo Receiver 2.4G/2.5G/800Mbps/166MHz 8-Lane
- Camera SLVS-EC/sub-LVDS/CMOS1.8 combo Receiver 2.4G/800Mbps/166MHz 8-Lane
- Camera Sub-LVDS Receiver
- Camera sub-LVDS/mini-LVDS/LVDS/HiSPi(SLVS-400, HiVCM)/MIPI-DPHY/CMOS 6-7mode Combo-Receiver 1.5Gbps
- Camera MIPI D-PHY v1-1 1.5Gbps / sub-LVDS combo Receiver 4-Lane