The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream. This serial stream clarifies the move of 12-bit or less bus over PCB finds and cables by removing the skew problems between parallel data and clock paths.Each transmitter takes a single-ended input, and generates an LVDS differential output. The receiver, on the other hand, accepts an LVDS input signal at low voltage levels and converts it into a single-ended signal.In addition, this SERDES pair has built-in system and device test capability.
The line loopback characteristics allows a user to check the probity of the serial data transmission path of the transmitter and receiver while deserializing the serial data to parallel data at the receiver output.
- Low power dissipation
- Integrated termination resistors in transmitter and receiver.
- Level Shifting and single-ended to differential conversion included
- Wide reference clock frequency tolerance: +/-500ppm
- Internal PLL, no external PLL components are required
- >2.0kV HBM ESD
- Full industrial operating temperature range: -40 ~ +125 °C
- Programmable pre-emphasis (0dB / 3dB / 6dB / 9dB)
- Compatible with the TIA/EIA-644-A LVDS standard
- Modular design to facilitate customization and process migration
- Can be easily integrated into multiple Channels
- Data Sheet
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R