The CL12481IP transmitter converts parallel 35bits (30bits of RGB data and 5bits of HSYNC, VSYNC, DE and Control1, Control2) of LVCMOS data into serial 5-LVDS data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a sixth LVDS link. The CL12481IP transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of LCD timing and control data (HSYNC, VSYNC, DE, Control1, Control2) are transmitted at a rate of 945Mbps per LVDS data channel. The CL12481IP transmitter is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.
- Input Clock: 20MHz~135MHz (max: 170MHz) shift clock support
- Output Clock: 20MHz to 135MHz (max: 170MHz)
- Output Data Rate: 140Mbps~945Mbps (max: 1.19Gbps)
- Low power single 3.3V (Option: 2.8V)
- TIA/EIA-644 and IEEE 1596.3 compliant
- Clock edge programmable
- Supports RGB 18 / 24 / 30
- Narrow bus reduces cable size
- PLL requires no external components
- Power down mode
- ±345mV swing LVDS for low EMI
- Supports 200mV Differential Amplitude Outputs
- Pin Compatible with THine THC63LVD103
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP from this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file