VISENGI's JPEG Decoder IP core has been developed to be a complete standards compliant M-JPEG Hardware Decoder.
- Baseline DCT decoder according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard
- Seamless Motion JPEG (MJPEG) decoding
- Dual pixel output for top speed (4 pixels decoded every 3 cycles)
- Industry standard AXI interfaces (AXI and AXI4-stream for row-wise output)
- Plug and Play IP blocks for Xilinx Vivado and Altera Quartus Qsys
- No need for external CPU or memory.
- Unlimited image size (specification up to 64K x64K)
- Maximum number of Huffman and Quantization tables allowed by specification (four each)
- Allows RST (restart intervals) and DNL (for multi-scan images) markers
- Selectable YCbCr and/or RGB output
- Throughput: up to 4 pixels output every 3 clock cycles
- VISENGI's JPEG Decoder features a dual pixel component pipeline, allowing for greater decoding speeds. And what is more important, a highly optimized Huffman decoder has been designed and fine tuned into the system.
- These two features coupled make our JPEG Decoder unique in guaranteeing decoding speed even for the highest quality images (worst compression ratios), while other decoders can only sustain their throughputs at lower qualities and just advertise their maximum speed.
- Technical support
- Documentation and design examples
- Altera and Xilinx IP blocks
- Instantation Templates